About

Systolic Array-Based CNN Accelerator for Gesture Recognition

Designed a pure-hardware INT8 CNN accelerator ASIC for 64x64 grayscale gesture recognition in 65 nm, including a 64-PE systolic array, on-chip SRAM architecture, full RTL implementation, synthesis, place-and-route, timing closure, and post-layout verification.

• Architected a compute-and-memory pipeline around a systolic array and local SRAM buffering for efficient CNN inference.
• Completed the end-to-end digital flow from RTL to backend implementation and signoff-oriented analysis.
• Co-optimized model structure and hardware cost for a gesture-recognition tape-out project.

This tape-out project is still in progress. The linked datasheet captures an early architectural concept and does not reflect the final scope or outcome of the project. The public repository currently contains only the CNN training and quantization flow, not the RTL implementation.

Out-of-Order RISC-V Processor

Designed a P6-style out-of-order RISC-V microarchitecture with a reorder buffer, register alias table, reservation stations, physical register file, precise commit, speculative recovery support, and multi-stage execution coordination across the pipeline.

• Implemented core OoO structures including register renaming, reservation-station scheduling, ROB-based commit, and branch-misprediction recovery logic.
• Designed the interaction between issue, execute, writeback, and commit stages to maintain precise architectural state under speculation.
• Worked through data hazards, dependency tracking, and rollback behavior to better understand performance-oriented CPU microarchitecture.
• Used the project to connect classroom architecture concepts with concrete RTL-level control and datapath design decisions.

This processor project is still a work in progress, and the current description reflects the architecture and implementation scope completed so far.

64-Tap 16-Bit FIR Digital Filter Core

Designed a fixed-point FIR core with a multiply-accumulate datapath, CMEM/IMEM, FSM-based controller, and a dual-clock FIFO for clock-domain crossing. Completed RTL, synthesis, STA, and post-synthesis verification.

• Built a complete digital signal-processing pipeline around a parameterized FIR core.
• Integrated dual-clock FIFO logic to handle CDC between low-speed input and high-speed compute domains.
• Validated the design through synthesis and timing analysis using industry-standard EDA tools.

Formal Verification of an N-Body Hardware Accelerator

Wrote SVA assertions, assumptions, and cover properties in JasperGold to verify FSM transitions, loop-control behavior, and pointer bounds, uncovering corner-case bugs not exposed by simulation.

• Developed property sets for safety, liveness, and legal state progression.
• Used formal methods to expose corner cases that would be difficult to hit with directed simulation alone.
• Strengthened understanding of hardware correctness beyond waveform-based debugging.

8-Bit Microcontroller Core Design

Completed transistor-level design of an accumulator-based 8-bit microcontroller in TSMC 65 nm using a custom 6-bit ISA, including schematic, layout, verification, and post-layout analysis.

• Implemented key modules including PLA control logic, accumulator, adder, shifter, memory latch, bus driver, and 8-byte SRAM.
• Achieved DRC/LVS-clean layout and verified ADD, SHIFT, and full-processor behavior in both pre-layout and post-layout simulation.
• Completed post-layout analysis with a 354 ps critical path and a core area of about 7267.49 um2.

High-Precision SAR ADC Design and Digital Calibration

Joined Associate Professor Xing Xinpeng's research group in senior year to design and verify a capacitor-mismatch digital calibration scheme for a 0.18 um 16-bit SAR ADC.

• Built a MATLAB behavioral model including capacitor mismatch, comparator noise, and other non-idealities to compare foreground calibration and dither-injection LMS calibration.
• Implemented and tested the calibration module on FPGA to evaluate both calibration effectiveness and hardware overhead.
• Improved ENOB from 9.97 bits to 15.67 bits under 3 percent CDAC mismatch.

8-Bit 10 GSPS Time-Interleaved SAR ADC

Participated in the National College IC Innovation and Entrepreneurship Competition and designed an 8-bit 10 GSPS time-interleaved SAR ADC in TSMC 40 nm.

• Completed literature review and architecture analysis, then selected a 16-channel TI-SAR solution with 625 MHz sampling rate per channel.
• Designed and optimized the single-channel SAR ADC in Cadence Virtuoso, including low-power DAC switching, high-linearity sampling switch, low-noise dynamic comparator, and adaptive asynchronous SAR logic.
• Integrated the 16-channel time-interleaved architecture and completed pre-layout verification across input frequencies, process corners, and temperatures.

FPGA-Based Portable Electronic Test System

Built a portable electronic test system integrating a signal generator and oscilloscope on FPGA, and received a university-level excellence award.

• Developed the signal-generator module using DDS to generate adjustable waveform signals.
• Integrated oscilloscope functionality with FFT-based spectrum analysis for signal observation and characterization.
• Took primary responsibility for the signal-generator module and final system integration.